From MAILER-DAEMON@eli.wariat.org Wed Oct 2 20:53:55 1996 Received: from localhost (localhost) by eli.wariat.org (8.7.5/8.7.3) with internal id UAA03184; Wed, 2 Oct 1996 20:53:55 -0500 Date: Wed, 2 Oct 1996 20:53:55 -0500 From: Mail Delivery Subsystem Subject: Returned mail: User unknown Message-Id: <199610030153.UAA03184@eli.wariat.org> To: miscarc@eli.wariat.org MIME-Version: 1.0 Content-Type: multipart/report; report-type=delivery-status; boundary="UAA03184.844307635/eli.wariat.org" Auto-Submitted: auto-generated (failure) This is a MIME-encapsulated message --UAA03184.844307635/eli.wariat.org The original message was received at Wed, 2 Oct 1996 20:53:50 -0500 from miscarc@localhost ----- The following addresses have delivery notifications ----- MISC@pisa.rockefeller.edu (unrecoverable error) ----- Transcript of session follows ----- ... while talking to pisa.rockefeller.edu.: >>> RCPT To: <<< 550 ... User unknown 550 MISC@pisa.rockefeller.edu... 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User unknown Last-Attempt-Date: Wed, 2 Oct 1996 20:53:53 -0500 --UAA03184.844307635/eli.wariat.org Content-Type: message/rfc822 Return-Path: miscarc Received: (from miscarc@localhost) by eli.wariat.org (8.7.5/8.7.3) id UAA03183; Wed, 2 Oct 1996 20:53:50 -0500 Date: Wed, 2 Oct 1996 20:53:50 -0500 Message-Id: <199610030153.UAA03183@eli.wariat.org> From: MISC Minimal Instruction Set Computers Archive To: MISC@pisa.rockefeller.edu CC: rj@eli.wariat.org Subject: subscribe SUBSCRIBE miscarc@eli.wariat.org "MISC Archives" --UAA03184.844307635/eli.wariat.org-- From MISC-request@pisa.rockefeller.edu Sun Oct 6 22:46:38 1996 Received: from rockvax.rockefeller.edu (rockvax.rockefeller.edu [129.85.1.21]) by eli.wariat.org (8.7.5/8.7.3) with ESMTP id WAA05588; Sun, 6 Oct 1996 22:46:36 -0500 Received: from pisa.rockefeller.edu (pisa.rockefeller.edu [129.85.23.103]) by rockvax.rockefeller.edu (8.7.4/8.7.4) with SMTP id XAA06153; Sun, 6 Oct 1996 23:45:30 -0400 (EDT) Received: by pisa.rockefeller.edu (940816.SGI.8.6.9/940406.SGI) id XAA10113; Sun, 6 Oct 1996 23:45:39 -0400 X-Received: from pisa.rockefeller.edu by venezia.rockefeller.edu via ESMTP (940816.SGI.8.6.9/940406.SGI) for id XAA12568; Sun, 6 Oct 1996 23:42:57 -0400 X-Received: by pisa.rockefeller.edu (940816.SGI.8.6.9/940406.SGI) for penev id XAA10071; Sun, 6 Oct 1996 23:42:56 -0400 Date: Sun, 6 Oct 1996 23:42:56 -0400 Old-X-Envelope-From: penev@venezia Sun Oct 6 23:42:53 1996 X-Received: from venezia.rockefeller.edu by pisa.rockefeller.edu via ESMTP (940816.SGI.8.6.9/940406.SGI) for id XAA10064; Sun, 6 Oct 1996 23:42:53 -0400 X-Received: from venezia.rockefeller.edu by venezia.rockefeller.edu via SMTP (940816.SGI.8.6.9/940406.SGI) for id XAA12565; Sun, 6 Oct 1996 23:42:52 -0400 Newsgroups: comp.lang.forth Old-Date: Sun, 6 Oct 1996 23:42:45 -0400 (EDT) From: Penio Penev To: MISC@pisa.rockefeller.edu Subject: The MISC mailing list is back In-Reply-To: Message-ID: References: <32549922.3B82@bbs.wa4yse.ampr.org> <3255E57B.28D7@bbs.wa4yse.ampr.org> MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII ReSent-Date: Sun, 6 Oct 1996 23:45:28 -0400 (EDT) ReSent-From: Penio Penev ReSent-To: MISC@pisa.rockefeller.edu ReSent-Message-ID: X-Mailing-List: archive/latest/391 X-Loop: MISC@pisa.rockefeller.edu Precedence: list Resent-Sender: MISC-request@pisa.rockefeller.edu On Sat, 5 Oct 1996, Jeff Fox wrote: > A couple of years ago we had about 100 people asking these same > questions either here or in email to me. In order to not take > up bandwidth in comp.lang.forth about MISC hardware details > and errata we set up the MISC mail list which has about 200 > people in it now. > > The MISC mail list and Penio's other accounts are not in operation > at the moment. I am happy to announce that the MISC mailing list is back after the recovery of a crash with sparks off the power supply of the machine. To access the list from the web, visit http://pisa.rockefeller.edu:8080/MISC/ To subscribe, send email to MISC-request@pisa.rockefeller.edu with the word 'subscribe' in the Subject: . > When they are revived or moved somewhere else > you can check the archives and the discussions of these people > about P21 and other MISC experiences. > I really don't have the time to answer all of your questions > here, so I think you may have to wait to get into the MISC archives. Be welcome to check them out, -- Penio Penev 1-212-327-7423 From MISC-request@pisa.rockefeller.edu Mon Oct 7 21:43:50 1996 Received: from rockvax.rockefeller.edu (rockvax.rockefeller.edu [129.85.1.21]) by eli.wariat.org (8.7.5/8.7.3) with ESMTP id VAA16118; Mon, 7 Oct 1996 21:43:48 -0500 Received: from pisa.rockefeller.edu (pisa.rockefeller.edu [129.85.23.103]) by rockvax.rockefeller.edu (8.7.4/8.7.4) with SMTP id WAA10094; Mon, 7 Oct 1996 22:42:16 -0400 (EDT) Received: by pisa.rockefeller.edu (940816.SGI.8.6.9/940406.SGI) id WAA13022; Mon, 7 Oct 1996 22:42:38 -0400 Resent-Date: Mon, 7 Oct 1996 22:42:38 -0400 From: Wayne Morellini Message-Id: <199610080232.MAA24780@cq-pan.cqu.EDU.AU> Subject: Re:Misc Mailing List is Back To: misc@pisa.rockefeller.edu Date: Tue, 8 Oct 1996 12:32:33 +1000 (EST) X-Mailer: ELM [version 2.4 PL24] MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Resent-Message-ID: <"L-y7B1.0.MB3.Q-RMo"@pisa> Resent-From: MISC@pisa.rockefeller.edu X-Mailing-List: archive/latest/392 X-Loop: MISC@pisa.rockefeller.edu Precedence: list Resent-Sender: MISC-request@pisa.rockefeller.edu Penio Penev wrote: >On Sat, 5 Oct 1996, Jeff Fox wrote: > >> A couple of years ago we had about 100 people asking these same >> questions either here or in email to me. In order to not take >> up bandwidth in comp.lang.forth about MISC hardware details >> and errata we set up the MISC mail list which has about 200 >> people in it now. >> >> The MISC mail list and Penio's other accounts are not in operation >> at the moment. > >I am happy to announce that the MISC mailing list is back after the >recovery of a crash with sparks off the power supply of the machine. > >To access the list from the web, visit >http://pisa.rockefeller.edu:8080/MISC/ > >To subscribe, send email to MISC-request@pisa.rockefeller.edu with the >word 'subscribe' in the Subject: . > >> When they are revived or moved somewhere else >> you can check the archives and the discussions of these people >> about P21 and other MISC experiences. > >> I really don't have the time to answer all of your questions >> here, so I think you may have to wait to get into the MISC archives. > >Be welcome to check them out, > >-- >Penio Penev 1-212-327-7423 > Well the amount of traffic has been almost minimal since about this time last year. I'm surprised there are that many people on the list, I thought the list must have been dead from lack of interest. I mean I have a number of times quieried misc-request to see if it was still up, or that I had been acidentally de-registered by the system due to no traffic. So to spark some interest it would help if we got regular updates from the people behind the processors p21, F-21, I21 (Yes I still know how to get to the page with I21 press release on Jeffs Web site that says it will be available for licencing etc, despite the denial of ITV when I enquired, despite Jeff removing the new pages a day or two after I origionally saw them), and THE 32-BIT P32. Announcements of products would be good too. Wayne Morellini waynem1@cq-pan.cqu.edu.au -- From MISC-request@pisa.rockefeller.edu Tue Oct 8 12:45:15 1996 Received: from rockvax.rockefeller.edu (rockvax.rockefeller.edu [129.85.1.21]) by eli.wariat.org (8.7.5/8.7.3) with ESMTP id MAA00445; Tue, 8 Oct 1996 12:45:12 -0500 Received: from pisa.rockefeller.edu (pisa.rockefeller.edu [129.85.23.103]) by rockvax.rockefeller.edu (8.7.4/8.7.4) with SMTP id NAA16798; Tue, 8 Oct 1996 13:44:13 -0400 (EDT) Received: by pisa.rockefeller.edu (940816.SGI.8.6.9/940406.SGI) id NAA14714; Tue, 8 Oct 1996 13:44:22 -0400 Resent-Date: Tue, 8 Oct 1996 13:44:22 -0400 Date: Tue, 8 Oct 1996 19:41:55 +0200 (MET DST) From: Eugene Leitl X-Sender: ui22204@sun2 To: misc Cc: Jeff Fox Subject: Re: The MISC mailing list is back Message-Id: Mime-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Resent-Message-ID: <"Dr2p-2.0.rb3.pBfMo"@pisa> Resent-From: MISC@pisa.rockefeller.edu X-Mailing-List: archive/latest/393 X-Loop: MISC@pisa.rockefeller.edu Precedence: list Resent-Sender: MISC-request@pisa.rockefeller.edu Thanks god! I almost thought something very bad (even worse than abovementioned system casualty) has happened. I have been unable to reach Jeff/Chuck lately, had anybody more luck? Any inside info, how the iTv box is progressing, somebody? In http://www.dnai.com/~jfox/f21stat.html it is stated: "A limited number of F21b prototype chips and F21 PCBv1 are available from Ultra Technology". Has anybody ordered/used these? What was your experience so far? I have built a POP biotracker, a wearable (D)GPS/biosignature telemetry device. Now I'd like to build a fully working prototype. However, as the project financers are pushing for speed, and there are different (non-FORTH :(( developer fraction in the tentative team, I am somewhat strained in legitimizing my indended use of Forth/MISC/F21. I believe need a true killer demo. I'd very like to make it a true MISC Forth box. However, the F21 developer board is still not available, so I consider starting on the Dr. Ting's MuP21 board. Alas, I have not found any details about this beast. An URL, anybody? What I need: - a PAL output (NTSC is useless in Europe, I know MuP21 can do PAL in theory) - a standard PC keyboard input - a serial port (best 2 x RS232, but I'd settle for one) - some kind of mass storage, e.g. a flash memory card - some digital I/O lines - a small prototype area (optional) Does the Offete system qualify? Thanks a lot in advance, -- Eugene From MISC-request@pisa.rockefeller.edu Tue Oct 8 13:01:53 1996 Received: from rockvax.rockefeller.edu (rockvax.rockefeller.edu [129.85.1.21]) by eli.wariat.org (8.7.5/8.7.3) with ESMTP id NAA00474; Tue, 8 Oct 1996 13:01:50 -0500 Received: from pisa.rockefeller.edu (pisa.rockefeller.edu [129.85.23.103]) by rockvax.rockefeller.edu (8.7.4/8.7.4) with SMTP id NAA18081; Tue, 8 Oct 1996 13:59:59 -0400 (EDT) Received: by pisa.rockefeller.edu (940816.SGI.8.6.9/940406.SGI) id OAA15116; Tue, 8 Oct 1996 14:00:13 -0400 Resent-Date: Tue, 8 Oct 1996 14:00:13 -0400 Date: Tue, 8 Oct 1996 19:59:04 +0200 (MET DST) From: Eugene Leitl X-Sender: ui22204@sun2 To: Wayne Morellini Cc: misc@pisa.rockefeller.edu Subject: Re:Misc Mailing List is Back In-Reply-To: <199610080232.MAA24780@cq-pan.cqu.EDU.AU> Message-Id: Mime-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Resent-Message-ID: <"CDr7H.0.4i3.eQfMo"@pisa> Resent-From: MISC@pisa.rockefeller.edu X-Mailing-List: archive/latest/394 X-Loop: MISC@pisa.rockefeller.edu Precedence: list Resent-Sender: MISC-request@pisa.rockefeller.edu On Tue, 8 Oct 1996, Wayne Morellini wrote: > Penio Penev wrote: > > ... > > Well the amount of traffic has been almost minimal since about this time > last year. I'm surprised there are that many people on the list, I thought Traffic? Which traffic? > the list must have been dead from lack of interest. I mean I have a number > of times quieried misc-request to see if it was still up, or that I had been > acidentally de-registered by the system due to no traffic. This is what I also thought. > > So to spark some interest it would help if we got regular updates from the > people behind the processors p21, F-21, I21 (Yes I still know how to get to Indeed. I also, happen to be somewhat bitter about this lamentable lack of information on chip progress. I mean: FORTH is pretty exotic already, must this be further aggravated by lack of user support? With virtually no data sheets I can live with. But relying on on a single source, with no detailed information nor progress info forthcoming, while in dire need to choose a reliable hardware platform to develop a product? Scusi, but I am not mad. If this goes on for some more time, I have to choose an off-shelf embedded controller. My financers won't wait much longer. This will exclude the Forth option, but it will keept the product alive. > the page with I21 press release on Jeffs Web site that says it will be > available for licencing etc, despite the denial of ITV when I enquired, I think i21 won't, but F21 will (provided, I'll ever live to see it). > despite Jeff removing the new pages a day or two after I origionally saw > them), and THE 32-BIT P32. Announcements of products would be good too. Seconded fully. Eugene Leitl > Wayne Morellini > waynem1@cq-pan.cqu.edu.au > > -- > > _________________________________________________________________________________ | mailto: ui22204@sunmail.lrz-muenchen.de | transhumanism >H, cryonics, | | mailto: Eugene.Leitl@uni-muenchen.de | nanotechnology, etc. etc. | | mailto: c438@org.chemie.uni-muenchen.de | "deus ex machina, v.0.0.alpha" | | icbmto: N 48 10'07'' E 011 33'53'' | http://www.lrz-muenchen.de/~ui22204 | From MISC-request@pisa.rockefeller.edu Tue Oct 8 14:20:37 1996 Received: from rockvax.rockefeller.edu (rockvax.rockefeller.edu [129.85.1.21]) by eli.wariat.org (8.7.5/8.7.3) with ESMTP id OAA00699; Tue, 8 Oct 1996 14:20:31 -0500 Received: from pisa.rockefeller.edu (pisa.rockefeller.edu [129.85.23.103]) by rockvax.rockefeller.edu (8.7.4/8.7.4) with SMTP id PAA24778; Tue, 8 Oct 1996 15:18:54 -0400 (EDT) Received: by pisa.rockefeller.edu (940816.SGI.8.6.9/940406.SGI) id PAA16173; Tue, 8 Oct 1996 15:19:18 -0400 Resent-Date: Tue, 8 Oct 1996 15:19:18 -0400 Date: Tue, 8 Oct 1996 14:18:46 -0500 Message-Id: <199610081918.OAA00687@eli.wariat.org> From: "Robert J. Brown" To: MISC@pisa.rockefeller.edu Subject: MISC Archive in HTML format Resent-Message-ID: <"Kp-c-.0.ey3.pagMo"@pisa> Resent-From: MISC@pisa.rockefeller.edu X-Mailing-List: archive/latest/395 X-Loop: MISC@pisa.rockefeller.edu Precedence: list Resent-Sender: MISC-request@pisa.rockefeller.edu The MISC mailing list is now being archived automatically by MHonarc producing a web browsable mailing list archive. This new service is available at: http://eli.wariat.org/miscarc/index.html Enjoy! -- -------- "And there came a writing to him from Elijah" [2Ch 21:12] -------- Robert Jay Brown III rj@eli.wariat.org http://eli.wariat.org 1 847 705-0424 Elijah Laboratories Inc.; 37 South Greenwood Avenue; Palatine, IL 60067-6328 ----- M o d e l i n g t h e M e t h o d s o f t h e M i n d ------ From MISC-request@pisa.rockefeller.edu Tue Oct 8 16:59:05 1996 Received: from rockvax.rockefeller.edu (rockvax.rockefeller.edu [129.85.1.21]) by eli.wariat.org (8.7.5/8.7.3) with ESMTP id QAA01467; Tue, 8 Oct 1996 16:59:01 -0500 Received: from pisa.rockefeller.edu (pisa.rockefeller.edu [129.85.23.103]) by rockvax.rockefeller.edu (8.7.4/8.7.4) with SMTP id RAA05760; Tue, 8 Oct 1996 17:58:00 -0400 (EDT) Received: by pisa.rockefeller.edu (940816.SGI.8.6.9/940406.SGI) id RAA16968; Tue, 8 Oct 1996 17:58:21 -0400 Resent-Date: Tue, 8 Oct 1996 17:58:21 -0400 Date: Tue, 8 Oct 1996 14:57:25 -0700 From: jfox@netcom.com (Jeff Fox) Message-Id: <199610082157.OAA03554@netcom19.netcom.com> To: MISC@pisa.rockefeller.edu Subject: Offete_News Resent-Message-ID: <"jDiFV3.0.394.wviMo"@pisa> Resent-From: MISC@pisa.rockefeller.edu X-Mailing-List: archive/latest/396 X-Loop: MISC@pisa.rockefeller.edu Precedence: list Resent-Sender: MISC-request@pisa.rockefeller.edu Dear MISC readers: Yesterday I got the following mail from Dr. C.H. Ting : From TingCH@ccmail.apldbio.com Mon Oct 7 10:53:39 1996 Subject: Forth Engines Dear Forth Engine User: More On Forth Engines, Volume 21 is now published. Time really can fly. It is almost a year since the last volume was published last September. It is not that there have been very few things happening in the field of Forth engines. Actually, there are too many things happening. I have too many balls in the air and I was waiting them to settle down a bit so I can sit down and record the activities. The most interesting is of course what Chuck Moore is doing. He's been working on a series of Forth chips on the basis he laid out in MuP21. The chips realized in silicon, as I remember, included P8, F21, V21, and currently I21. P32 is in the serious thinking stage. When we worked on P21, the goal was to get the chip working, and lots of ideas were put off. When P21 was done, the lid was blown off and a tremendous among of creative energy was release in the newer designs. Chuck changed every transistor, moved everything around and experimenting with new control strategies. He is pretty happy with the current design of I21, and the prototype chips worked fairly well, it displayed some very crispy pictures on a color monitor. I21 is being developed by iTv Corp. Its goal is to produce a low cost Internet ready computer for home use. I21 connects TV, phone, and a keyboard together to allow the user to surf Internet conveniently in a home entertainment environment. It attracted substantial investments and assembled a high power team of Forth programmers to produce the system. At the beginning of this year, I visited Taiwan for a Forth Workshop. There I kind of committed myself to three projects: the first is to produce a system for the MuP21H chip in the 44-pin PLCC package, the second was to help marketing the CT100 microcontroller teaching/prototyping kit, and the third was to replace the BIOS chip on 486 motherboard to build very cheap but very powerful embedded processing systems. I wanted to report the results of these projects in this volume. This is the reason why this volume is delayed for so long. The new MuP21H kit uses a 82C51 UART chip to handle the serial communication with the host PC. There are many intriguing properties in 82C51 which ware not fully understood when I first laid out the PCB for it. Consequently the first board didn't work. After I ironed out all the bugs, the second layout worked perfectly. Now we can use this system to do serious programming, using a PC as the terminal server and file server. It is interesting to note that MuP21 is very close to an Internet computer, because of its video coprocessor and the very versatile I/O bus. Hooking an UART to it is only a simple demonstration of what it can do. As the DRAM price collapsed, as it should have years ago, the price of assembled MuP21 kit is also lowered from $350 to $250. Hope this price reduction will encourage you to try out this very exciting microprocessor. It is the only microprocessor which can generate video by itself. The CT100 Lab Board is an 8051 based microcontroller laboratory which contains about 20 different circuit groups for experiments on microcontroller programming and interfacing. You connect the circuit groups with jumper cables and are ready to write software to exercise the hardware. It is a great tool to teach microcontrollers. As the 8051 is driven by a F83 system, Forth is the natural language to develop software on this system. I was so impressed by this system that I promised to develop a teaching course for it. It took a while, but I finished building the course and also wrote a manual for it. I like to market it in the US. I think it is a great tool to train people in microcontroller programming and Forth, of course. I had more troubles than what I asked for in trying to replace BIOS with Forth. The vision was that 486 motherboards are become so cheap that they are now the cheapest and most powerful embedded system money can buy. For $100, you can get a 486 board with 1 MB of DRAM, 2 serial ports, 1 parallel port, a floppy controller, and a IDE hard disk controller, on an a single piece of PCB. My goal was to put an eForth in the BIOS socket and I could have a powerful computing element, which can be used as a node in a parallel computing system. 486 microprocessor is interesting because of the 32-bit linear addressing space in the protected mode, and the powerful floating point math coprocessor. If I can link 10 or 100 of these beasts together, I could have a super computer on my desk. The progress was slow and tedious. I threw away the DOS extender I used in the 386 eForth, V1.01, because the DOS extender itself is too complicated and not suitable for ROMming. I used Chuck's OK as the protected mode loader and get the eForth to work well in the 32-bit protected mode, entered from DOS. However, all attempts to replace BIOS ROM failed. The logic analyzer showed that the first subroutine call failed to return to the caller. Investigating code in BIOS made me feel hopeless because different motherboards use different chip sets which are initialized differently by different BIOS chips. It is apparently impossible to build a Forth which can deal with all the motherboard in a uniform way. The next best approach was to replace the Video BIOS ROM on the video display card. This can be done uniformly, because the motherboard BIOS calls the Video BIOS after the motherboard is completely initialized, and that the Video BIOS is always located at C0000H. This strategy worked, and I was able to boot up eForth on a bare-bone 486 motherboard with an Award BIOS ROM. We still need to test it on other motherboards. You will find reports on these three project in this volume. In addition I included two papers I presented at the 1996 Rochester Forth Conference held in Toronto in June. Laws of Computing tries to summarize the principles of programming and prove that Forth is the best programming language. We all know that, but it is nice to prove it from the first principles. Now, we have the first principles and the proof. Traffic Controller and Zen of State Machine is my answer to the Programming challenger presented at the Forth Day Conference at the Silicon Valley FIG Chapter. The most amazing discovery was that Forth is the perfect language to program state machines. No new words or new concept outside the F-PC are necessary. Remember ShBoom? It is now being developed by Patriot Scientific Corporation in Poway, CA. George Shaw was invited to SVFIG to talk about it and he distributed data sheets, which are reproduced here. Klaus Schleisiek also visited SVFIG and gave a talk on his new Forth chip IX. His handout is also included. Several users requested RTX processor and it reminded me what a nice microprocessor it is. I am still distributing the RTX kit. If you have an application which requires fast and precisely timed reponse from the computer, RTX with cmForth is still the best answer. Just before the Volume 21 goes to the printer, I worked out the logic design of a 16 bit microprocessor P16, modeled after Chuck Moore's MuP21. A paper is appended to the end of this volume. P16 design is in standard schematics and had passed logic simulation. It demonstrates my understanding of the P21 architecture and its logic operations. Dr. C. H. Ting Offete Enterprise San Mateo, California 1306 South B Street October, 1996 San Mateo, CA 94402 (415)574-8250, Fax (415)571-5004 New Products from Offete Enterprises: 4121 More on Forth Engines, Volume 21, $20 Editor's Notes New products from Offete Enterprises MuP21H Kit My Troubles with This Darn 82C51 CT100 Lab Board Born to be Free Laws of Computing Traffic Controller and Zen of State Machines ShBoom Microprocessor Programmable Fieldbus Controller IX1 Logic Design of a 16-Bit Microprocessor P16 4018 MuP21H Chip in PLCC, $40 MuP21 is now available in 44-pin PLCC packages. It has much smaller (1/3) footprint compared to DIP, and is suitable for surface mount.. 4019 MuP21H Evaluation Kit, $100 Include PLCC MuP21H, a printed circuit board, a 128KB EPROM with eForth V2.08, instructions and assembler diskette. Build your own stand-alone MuP21 development system with 82C51 UART. 4020 Assembled MuP21H Evaluation Kit, $250 MuP21 system with 1Mx20 DRAM, 128KB EPROM eForth V2.08, and 82C51 UART to talk to PC host. Apply 5V power and it generates NTSC signals to drive a color TV monitor. Manual, MuP21 assembler and sample code included to guide application development. 4012 Assembled MuP21 Evaluation Kit, $350, $250 MuP21 system with 1Mx20 DRAM, 128KB EPROM, and 8-bit parallel I/O ports. Apply 5V power and it generates NTSC signals to drive a color TV monitor. Manual, MuP21 assembler and sample code included to guide application development. Note price reduction due to DRAM price drop. 1014 MuP21 Programming Manual, C. H. Ting-- $25.00 Second Edition with MuP21H update. Primary reference for MuP21 microprocessor. Architecture, instruction set, video coprocessor programming, assembler, bootstrap code, Chuck Moore's OK demonstration system, and his lectures on P21 and OK. 9008 CT-100 Lab Board, $400.00 This board is manufactured in Taiwan to train students in microcontroller interfacing. It has 8051 as the CPU, surrounded by interesting devices like LED and LCD displays, ADC, DAC, stepper motor controller, key array and keyboard, buzzer, etc. It provides enough materials for a one semester microcontroller course at college level. Students can get on to the experiments directly without having to worry about hardware assembly. Manual is available separately as Item #2132. 2132 CT100 Lab Board User Manual, C. H. Ting--$20.00 CT-100 is a 8051 based microcontroller training system, with integrated peripherals like LED and LCD displays, keys and keyboard input, ADC. DAC, stepper motor controller, relays, RS232, 8255, and 8279 peripherals. This manual details experiments using 8051 Forth to controller these devices. 2133 32-Bit 386 eForth V.4.02, C. H. Ting--$25.00 This is a 32 bit implementation of eForth for 80386 in the protected mode. It enters into protected mode directly without a DOS extender. Only COM1 is active at 9600 baud. Keyboard, screen and disks are all silenced. You need another PC to serve as a host through the serial port. 2134 32-Bit 386 eForth V.4.03, C. H. Ting--$25.00 This is a 32 bit implementation of eForth for 80386 in the protected mode. It replaces the Video BIOS at C0000H and booted by system BIOS. It converts a 386/486 motherboard to an embedded Forth processor, communicating with a PC through the COM1 port.. From MISC-request@pisa.rockefeller.edu Tue Oct 8 21:46:19 1996 Received: from rockvax.rockefeller.edu (rockvax.rockefeller.edu [129.85.1.21]) by eli.wariat.org (8.7.5/8.7.3) with ESMTP id VAA02387; Tue, 8 Oct 1996 21:46:17 -0500 Received: from pisa.rockefeller.edu (pisa.rockefeller.edu [129.85.23.103]) by rockvax.rockefeller.edu (8.7.4/8.7.4) with SMTP id WAA15717; Tue, 8 Oct 1996 22:45:03 -0400 (EDT) Received: by pisa.rockefeller.edu (940816.SGI.8.6.9/940406.SGI) id WAA17722; Tue, 8 Oct 1996 22:45:26 -0400 Resent-Date: Tue, 8 Oct 1996 22:45:26 -0400 From: Wayne Morellini Message-Id: <199610090235.MAA29146@cq-pan.cqu.EDU.AU> Subject: Re:Misc Mailing List is Back To: misc@pisa.rockefeller.edu Date: Wed, 9 Oct 1996 12:35:22 +1000 (EST) X-Mailer: ELM [version 2.4 PL24] MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Resent-Message-ID: <"mgf6_1.0.rK4.37nMo"@pisa> Resent-From: MISC@pisa.rockefeller.edu X-Mailing-List: archive/latest/397 X-Loop: MISC@pisa.rockefeller.edu Precedence: list Resent-Sender: MISC-request@pisa.rockefeller.edu Eugene Leitl wrote: >On Tue, 8 Oct 1996, Wayne Morellini wrote: > >> Penio Penev wrote: >> > ... >> >> Well the amount of traffic has been almost minimal since about this time >> last year. I'm surprised there are that many people on the list, I thought > >Traffic? Which traffic? A little bit begining of this year. > >> the list must have been dead from lack of interest. I mean I have a number >> of times quieried misc-request to see if it was still up, or that I had been >> acidentally de-registered by the system due to no traffic. > >This is what I also thought. > >> >> So to spark some interest it would help if we got regular updates from the >> people behind the processors p21, F-21, I21 (Yes I still know how to get to > >Indeed. I also, happen to be somewhat bitter about this lamentable lack >of information on chip progress. I mean: FORTH is pretty exotic already, >must this be further aggravated by lack of user support? With virtually >no data sheets I can live with. But relying on on a single source, with >no detailed information nor progress info forthcoming, while in dire need to >choose a reliable hardware platform to develop a product? Scusi, but I am >not mad. If this goes on for some more time, I have to choose an >off-shelf embedded controller. My financers won't wait much longer. > >This will exclude the Forth option, but it will keept the product alive. There are other Forth Processors the SC-32 from silicon composers, the Harris RTX-200x is still available but only limited versions. The Mup-21 is a good concept and I can sell you my kit. The others we are still waiting for, the Mup-21 execution has been reported to break after something like 100's of hours, but new packaging that was due soon this time last year and apart from requests nothing else has really been said about it to my knowledege, this packaging should fix a lot of problems, video resoluation isn't great 384*2xx. The F-21 and I-21 is supposed to be much better. > >> the page with I21 press release on Jeffs Web site that says it will be >> available for licencing etc, despite the denial of ITV when I enquired, > >I think i21 won't, but F21 will (provided, I'll ever live to see it). Like I21 like F-21, but wanted I21 type device. > >> despite Jeff removing the new pages a day or two after I origionally saw >> them), and THE 32-BIT P32. Announcements of products would be good too. > >Seconded fully. > >Eugene Leitl > Thanks Eugene. Wayne Morellini waynem1@cq-pan.cqu.edu.au -- From MISC-request@pisa.rockefeller.edu Tue Oct 8 21:59:47 1996 Received: from rockvax.rockefeller.edu (rockvax.rockefeller.edu [129.85.1.21]) by eli.wariat.org (8.7.5/8.7.3) with ESMTP id VAA02450; Tue, 8 Oct 1996 21:59:43 -0500 Received: from pisa.rockefeller.edu (pisa.rockefeller.edu [129.85.23.103]) by rockvax.rockefeller.edu (8.7.4/8.7.4) with SMTP id WAA16130; Tue, 8 Oct 1996 22:57:56 -0400 (EDT) Received: by pisa.rockefeller.edu (940816.SGI.8.6.9/940406.SGI) id WAA18101; Tue, 8 Oct 1996 22:58:19 -0400 Resent-Date: Tue, 8 Oct 1996 22:58:19 -0400 From: Wayne Morellini Message-Id: <199610090247.MAA01380@cq-pan.cqu.EDU.AU> Subject: Offete_News To: misc@pisa.rockefeller.edu Date: Wed, 9 Oct 1996 12:47:53 +1000 (EST) X-Mailer: ELM [version 2.4 PL24] MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Resent-Message-ID: <"SvDlA.0.jQ4.7JnMo"@pisa> Resent-From: MISC@pisa.rockefeller.edu X-Mailing-List: archive/latest/398 X-Loop: MISC@pisa.rockefeller.edu Precedence: list Resent-Sender: MISC-request@pisa.rockefeller.edu jfox@netcom.com (Jeff Fox) wrote: > >Dear MISC readers: > >Yesterday I got the following mail from Dr. C.H. Ting : > >>From TingCH@ccmail.apldbio.com Mon Oct 7 10:53:39 1996 >Subject: Forth Engines > >Dear Forth Engine User: > >More On Forth Engines, Volume 21 is now published. [snip] >He is pretty happy with the current >design of I21, and the prototype chips worked fairly well, it displayed some >very crispy pictures on a color monitor. This is what we need 256+ colour pictures, I mean 384 pixels accross is great in 16 colours, but if your going to make a micro-controller, you might have well given it an LCD interface instead otherwise, higher resolutions are better. > >I21 is being developed by iTv Corp. Its goal is to produce a low cost Internet >ready computer for home use. I21 connects TV, phone, and a keyboard together >to allow the user to surf Internet conveniently in a home entertainment >environment. It attracted substantial investments and assembled a high power >team of Forth programmers to produce the system. Money is ready, I'm still waiting otherwise I'll have to buy the 160Mhz Newton slate or the Webbook with the Sh-boom II chip. Eugene I forgot to mention this one in reply to your post. > >At the beginning of this year, I visited Taiwan for a Forth Workshop. There I >kind of committed myself to three projects: the first is to produce a system >for the MuP21H chip in the 44-pin PLCC package, the second was to help >marketing the CT100 microcontroller teaching/prototyping kit, and the third was >to replace the BIOS chip on 486 motherboard to build very cheap but very >powerful embedded processing systems. I wanted to report the results of these >projects in this volume. This is the reason why this volume is delayed for so >long. > >The new MuP21H kit uses a 82C51 UART chip to handle the serial communication >with the host PC. There are many intriguing properties in 82C51 which ware not >fully understood when I first laid out the PCB for it. Consequently the first >board didn't work. After I ironed out all the bugs, the second layout worked >perfectly. Now we can use this system to do serious programming, using a PC as >the terminal server and file server. It is interesting to note that MuP21 is >very close to an Internet computer, because of its video coprocessor and the >very versatile I/O bus. Hooking an UART to it is only a simple demonstration >of what it can do. 80 columns ) > >As the DRAM price collapsed, as it should have years ago, the price of >assembled MuP21 kit is also lowered from $350 to $250. Hope this price >reduction will encourage you to try out this very exciting microprocessor. It >is the only microprocessor which can generate video by itself. > >The CT100 Lab Board is an 8051 based microcontroller laboratory which contains >about 20 different circuit groups for experiments on microcontroller >programming and interfacing. You connect the circuit groups with jumper cables >and are ready to write software to exercise the hardware. It is a great tool >to teach microcontrollers. As the 8051 is driven by a F83 system, Forth is the >natural language to develop software on this system. I was so impressed by >this system that I promised to develop a teaching course for it. It took a >while, but I finished building the course and also wrote a manual for it. I >like to market it in the US. I think it is a great tool to train people in >microcontroller programming and Forth, of course. > >I had more troubles than what I asked for in trying to replace BIOS with Forth. >The vision was that 486 motherboards are become so cheap that they are now the >cheapest and most powerful embedded system money can buy. For $100, you can >get a 486 board with 1 MB of DRAM, 2 serial ports, 1 parallel port, a floppy >controller, and a IDE hard disk controller, on an a single piece of PCB. My >goal was to put an eForth in the BIOS socket and I could have a powerful >computing element, which can be used as a node in a parallel computing system. >486 microprocessor is interesting because of the 32-bit linear addressing space >in the protected mode, and the powerful floating point math coprocessor. If I >can link 10 or 100 of these beasts together, I could have a super computer on >my desk. > >The progress was slow and tedious. I threw away the DOS extender I used in the >386 eForth, V1.01, because the DOS extender itself is too complicated and not >suitable for ROMming. I used Chuck's OK as the protected mode loader and get >the eForth to work well in the 32-bit protected mode, entered from DOS. >However, all attempts to replace BIOS ROM failed. The logic analyzer showed >that the first subroutine call failed to return to the caller. Investigating >code in BIOS made me feel hopeless because different motherboards use different >chip sets which are initialized differently by different BIOS chips. It is >apparently impossible to build a Forth which can deal with all the motherboard >in a uniform way. > >The next best approach was to replace the Video BIOS ROM on the video display >card. This can be done uniformly, because the motherboard BIOS calls the Video >BIOS after the motherboard is completely initialized, and that the Video BIOS >is always located at C0000H. This strategy worked, and I was able to boot up >eForth on a bare-bone 486 motherboard with an Award BIOS ROM. We still need to >test it on other motherboards. > >You will find reports on these three project in this volume. In addition I >included two papers I presented at the 1996 Rochester Forth Conference held in >Toronto in June. Laws of Computing tries to summarize the principles of >programming and prove that Forth is the best programming language. We all know >that, but it is nice to prove it from the first principles. Now, we have the >first principles and the proof. Traffic Controller and Zen of State Machine is >my answer to the Programming challenger presented at the Forth Day Conference >at the Silicon Valley FIG Chapter. The most amazing discovery was that Forth >is the perfect language to program state machines. No new words or new concept >outside the F-PC are necessary. > >Remember ShBoom? It is now being developed by Patriot Scientific Corporation >in Poway, CA. George Shaw was invited to SVFIG to talk about it and he >distributed data sheets, which are reproduced here. Klaus Schleisiek also >visited SVFIG and gave a talk on his new Forth chip IX. His handout is also >included. > >Several users requested RTX processor and it reminded me what a nice >microprocessor it is. I am still distributing the RTX kit. If you have an >application which requires fast and precisely timed reponse from the computer, >RTX with cmForth is still the best answer. > >Just before the Volume 21 goes to the printer, I worked out the logic design of >a 16 bit microprocessor P16, modeled after Chuck Moore's MuP21. A paper is >appended to the end of this volume. P16 design is in standard schematics and >had passed logic simulation. It demonstrates my understanding of the P21 >architecture and its logic operations. > >Dr. C. H. Ting Offete Enterprise >San Mateo, California 1306 South B Street >October, 1996 San Mateo, CA 94402 > (415)574-8250, Fax (415)571-5004 > >New Products from Offete Enterprises: > >4121 More on Forth Engines, Volume 21, $20 >Editor's Notes >New products from Offete Enterprises >MuP21H Kit >My Troubles with This Darn 82C51 >CT100 Lab Board >Born to be Free >Laws of Computing >Traffic Controller and Zen of State Machines >ShBoom Microprocessor >Programmable Fieldbus Controller IX1 >Logic Design of a 16-Bit Microprocessor P16 > >4018 MuP21H Chip in PLCC, $40 >MuP21 is now available in 44-pin PLCC packages. It has much smaller (1/3) >footprint compared to DIP, and is suitable for surface mount.. >4019 MuP21H Evaluation Kit, $100 >Include PLCC MuP21H, a printed circuit board, a 128KB EPROM with eForth V2.08, >instructions and assembler diskette. Build your own stand-alone MuP21 >development system with 82C51 UART. >4020 Assembled MuP21H Evaluation Kit, $250 >MuP21 system with 1Mx20 DRAM, 128KB EPROM eForth V2.08, and 82C51 UART to talk >to PC host. Apply 5V power and it generates NTSC signals to drive a color TV >monitor. Manual, MuP21 assembler and sample code included to guide application >development. >4012 Assembled MuP21 Evaluation Kit, $350, $250 >MuP21 system with 1Mx20 DRAM, 128KB EPROM, and 8-bit parallel I/O ports. Apply >5V power and it generates NTSC signals to drive a color TV monitor. Manual, >MuP21 assembler and sample code included to guide application development. >Note price reduction due to DRAM price drop. >1014 MuP21 Programming Manual, C. H. Ting-- $25.00 >Second Edition with MuP21H update. Primary reference for MuP21 microprocessor. >Architecture, instruction set, video coprocessor programming, assembler, >bootstrap code, Chuck Moore's OK demonstration system, and his lectures on P21 >and OK. >9008 CT-100 Lab Board, $400.00 >This board is manufactured in Taiwan to train students in microcontroller >interfacing. It has 8051 as the CPU, surrounded by interesting devices like >LED and LCD displays, ADC, DAC, stepper motor controller, key array and >keyboard, buzzer, etc. It provides enough materials for a one semester >microcontroller course at college level. Students can get on to the >experiments directly without having to worry about hardware assembly. Manual >is available separately as Item #2132. >2132 CT100 Lab Board User Manual, C. H. Ting--$20.00 >CT-100 is a 8051 based microcontroller training system, with integrated >peripherals like LED and LCD displays, keys and keyboard input, ADC. DAC, >stepper motor controller, relays, RS232, 8255, and 8279 peripherals. This >manual details experiments using 8051 Forth to controller these devices. >2133 32-Bit 386 eForth V.4.02, C. H. Ting--$25.00 >This is a 32 bit implementation of eForth for 80386 in the protected mode. > It enters into protected mode directly without a DOS extender. Only COM1 is >active at 9600 baud. Keyboard, screen and disks are all silenced. You need >another PC to serve as a host through the serial port. >2134 32-Bit 386 eForth V.4.03, C. H. Ting--$25.00 >This is a 32 bit implementation of eForth for 80386 in the protected mode. > It replaces the Video BIOS at C0000H and booted by system BIOS. It converts >a 386/486 motherboard to an embedded Forth processor, communicating with a PC >through the COM1 port.. > > -- From rj@eli.wariat.org Wed Oct 9 00:07:09 1996 Received: (from rj@localhost) by eli.wariat.org (8.7.5/8.7.3) id AAA03464; Wed, 9 Oct 1996 00:07:08 -0500 Date: Wed, 9 Oct 1996 00:07:08 -0500 Message-Id: <199610090507.AAA03464@eli.wariat.org> From: "Robert J. Brown" To: miscarc@eli.wariat.org Subject: [jfox@netcom.com: Offete_News] ------- Start of forwarded message ------- Return-Path: MISC-request@pisa.rockefeller.edu Date: Tue, 8 Oct 1996 14:57:25 -0700 From: jfox@netcom.com (Jeff Fox) To: MISC@pisa.rockefeller.edu Subject: Offete_News Resent-From: MISC@pisa.rockefeller.edu X-Mailing-List: archive/latest/396 X-Loop: MISC@pisa.rockefeller.edu Precedence: list Resent-Sender: MISC-request@pisa.rockefeller.edu Dear MISC readers: Yesterday I got the following mail from Dr. C.H. Ting : From TingCH@ccmail.apldbio.com Mon Oct 7 10:53:39 1996 Subject: Forth Engines Dear Forth Engine User: More On Forth Engines, Volume 21 is now published. Time really can fly. It is almost a year since the last volume was published last September. It is not that there have been very few things happening in the field of Forth engines. Actually, there are too many things happening. I have too many balls in the air and I was waiting them to settle down a bit so I can sit down and record the activities. The most interesting is of course what Chuck Moore is doing. He's been working on a series of Forth chips on the basis he laid out in MuP21. The chips realized in silicon, as I remember, included P8, F21, V21, and currently I21. P32 is in the serious thinking stage. When we worked on P21, the goal was to get the chip working, and lots of ideas were put off. When P21 was done, the lid was blown off and a tremendous among of creative energy was release in the newer designs. Chuck changed every transistor, moved everything around and experimenting with new control strategies. He is pretty happy with the current design of I21, and the prototype chips worked fairly well, it displayed some very crispy pictures on a color monitor. I21 is being developed by iTv Corp. Its goal is to produce a low cost Internet ready computer for home use. I21 connects TV, phone, and a keyboard together to allow the user to surf Internet conveniently in a home entertainment environment. It attracted substantial investments and assembled a high power team of Forth programmers to produce the system. At the beginning of this year, I visited Taiwan for a Forth Workshop. There I kind of committed myself to three projects: the first is to produce a system for the MuP21H chip in the 44-pin PLCC package, the second was to help marketing the CT100 microcontroller teaching/prototyping kit, and the third was to replace the BIOS chip on 486 motherboard to build very cheap but very powerful embedded processing systems. I wanted to report the results of these projects in this volume. This is the reason why this volume is delayed for so long. The new MuP21H kit uses a 82C51 UART chip to handle the serial communication with the host PC. There are many intriguing properties in 82C51 which ware not fully understood when I first laid out the PCB for it. Consequently the first board didn't work. After I ironed out all the bugs, the second layout worked perfectly. Now we can use this system to do serious programming, using a PC as the terminal server and file server. It is interesting to note that MuP21 is very close to an Internet computer, because of its video coprocessor and the very versatile I/O bus. Hooking an UART to it is only a simple demonstration of what it can do. As the DRAM price collapsed, as it should have years ago, the price of assembled MuP21 kit is also lowered from $350 to $250. Hope this price reduction will encourage you to try out this very exciting microprocessor. It is the only microprocessor which can generate video by itself. The CT100 Lab Board is an 8051 based microcontroller laboratory which contains about 20 different circuit groups for experiments on microcontroller programming and interfacing. You connect the circuit groups with jumper cables and are ready to write software to exercise the hardware. It is a great tool to teach microcontrollers. As the 8051 is driven by a F83 system, Forth is the natural language to develop software on this system. I was so impressed by this system that I promised to develop a teaching course for it. It took a while, but I finished building the course and also wrote a manual for it. I like to market it in the US. I think it is a great tool to train people in microcontroller programming and Forth, of course. I had more troubles than what I asked for in trying to replace BIOS with Forth. The vision was that 486 motherboards are become so cheap that they are now the cheapest and most powerful embedded system money can buy. For $100, you can get a 486 board with 1 MB of DRAM, 2 serial ports, 1 parallel port, a floppy controller, and a IDE hard disk controller, on an a single piece of PCB. My goal was to put an eForth in the BIOS socket and I could have a powerful computing element, which can be used as a node in a parallel computing system. 486 microprocessor is interesting because of the 32-bit linear addressing space in the protected mode, and the powerful floating point math coprocessor. If I can link 10 or 100 of these beasts together, I could have a super computer on my desk. The progress was slow and tedious. I threw away the DOS extender I used in the 386 eForth, V1.01, because the DOS extender itself is too complicated and not suitable for ROMming. I used Chuck's OK as the protected mode loader and get the eForth to work well in the 32-bit protected mode, entered from DOS. However, all attempts to replace BIOS ROM failed. The logic analyzer showed that the first subroutine call failed to return to the caller. Investigating code in BIOS made me feel hopeless because different motherboards use different chip sets which are initialized differently by different BIOS chips. It is apparently impossible to build a Forth which can deal with all the motherboard in a uniform way. The next best approach was to replace the Video BIOS ROM on the video display card. This can be done uniformly, because the motherboard BIOS calls the Video BIOS after the motherboard is completely initialized, and that the Video BIOS is always located at C0000H. This strategy worked, and I was able to boot up eForth on a bare-bone 486 motherboard with an Award BIOS ROM. We still need to test it on other motherboards. You will find reports on these three project in this volume. In addition I included two papers I presented at the 1996 Rochester Forth Conference held in Toronto in June. Laws of Computing tries to summarize the principles of programming and prove that Forth is the best programming language. We all know that, but it is nice to prove it from the first principles. Now, we have the first principles and the proof. Traffic Controller and Zen of State Machine is my answer to the Programming challenger presented at the Forth Day Conference at the Silicon Valley FIG Chapter. The most amazing discovery was that Forth is the perfect language to program state machines. No new words or new concept outside the F-PC are necessary. Remember ShBoom? It is now being developed by Patriot Scientific Corporation in Poway, CA. George Shaw was invited to SVFIG to talk about it and he distributed data sheets, which are reproduced here. Klaus Schleisiek also visited SVFIG and gave a talk on his new Forth chip IX. His handout is also included. Several users requested RTX processor and it reminded me what a nice microprocessor it is. I am still distributing the RTX kit. If you have an application which requires fast and precisely timed reponse from the computer, RTX with cmForth is still the best answer. Just before the Volume 21 goes to the printer, I worked out the logic design of a 16 bit microprocessor P16, modeled after Chuck Moore's MuP21. A paper is appended to the end of this volume. P16 design is in standard schematics and had passed logic simulation. It demonstrates my understanding of the P21 architecture and its logic operations. Dr. C. H. Ting Offete Enterprise San Mateo, California 1306 South B Street October, 1996 San Mateo, CA 94402 (415)574-8250, Fax (415)571-5004 New Products from Offete Enterprises: 4121 More on Forth Engines, Volume 21, $20 Editor's Notes New products from Offete Enterprises MuP21H Kit My Troubles with This Darn 82C51 CT100 Lab Board Born to be Free Laws of Computing Traffic Controller and Zen of State Machines ShBoom Microprocessor Programmable Fieldbus Controller IX1 Logic Design of a 16-Bit Microprocessor P16 4018 MuP21H Chip in PLCC, $40 MuP21 is now available in 44-pin PLCC packages. It has much smaller (1/3) footprint compared to DIP, and is suitable for surface mount.. 4019 MuP21H Evaluation Kit, $100 Include PLCC MuP21H, a printed circuit board, a 128KB EPROM with eForth V2.08, instructions and assembler diskette. Build your own stand-alone MuP21 development system with 82C51 UART. 4020 Assembled MuP21H Evaluation Kit, $250 MuP21 system with 1Mx20 DRAM, 128KB EPROM eForth V2.08, and 82C51 UART to talk to PC host. Apply 5V power and it generates NTSC signals to drive a color TV monitor. Manual, MuP21 assembler and sample code included to guide application development. 4012 Assembled MuP21 Evaluation Kit, $350, $250 MuP21 system with 1Mx20 DRAM, 128KB EPROM, and 8-bit parallel I/O ports. Apply 5V power and it generates NTSC signals to drive a color TV monitor. Manual, MuP21 assembler and sample code included to guide application development. Note price reduction due to DRAM price drop. 1014 MuP21 Programming Manual, C. H. Ting-- $25.00 Second Edition with MuP21H update. Primary reference for MuP21 microprocessor. Architecture, instruction set, video coprocessor programming, assembler, bootstrap code, Chuck Moore's OK demonstration system, and his lectures on P21 and OK. 9008 CT-100 Lab Board, $400.00 This board is manufactured in Taiwan to train students in microcontroller interfacing. It has 8051 as the CPU, surrounded by interesting devices like LED and LCD displays, ADC, DAC, stepper motor controller, key array and keyboard, buzzer, etc. It provides enough materials for a one semester microcontroller course at college level. Students can get on to the experiments directly without having to worry about hardware assembly. Manual is available separately as Item #2132. 2132 CT100 Lab Board User Manual, C. H. Ting--$20.00 CT-100 is a 8051 based microcontroller training system, with integrated peripherals like LED and LCD displays, keys and keyboard input, ADC. DAC, stepper motor controller, relays, RS232, 8255, and 8279 peripherals. This manual details experiments using 8051 Forth to controller these devices. 2133 32-Bit 386 eForth V.4.02, C. H. Ting--$25.00 This is a 32 bit implementation of eForth for 80386 in the protected mode. It enters into protected mode directly without a DOS extender. Only COM1 is active at 9600 baud. Keyboard, screen and disks are all silenced. You need another PC to serve as a host through the serial port. 2134 32-Bit 386 eForth V.4.03, C. H. Ting--$25.00 This is a 32 bit implementation of eForth for 80386 in the protected mode. It replaces the Video BIOS at C0000H and booted by system BIOS. It converts a 386/486 motherboard to an embedded Forth processor, communicating with a PC through the COM1 port.. ------- End of forwarded message ------- From MISC-request@pisa.rockefeller.edu Wed Oct 9 08:33:38 1996 Received: from wariat.apk.net (root@wariat.wariat.org [192.147.147.1]) by eli.wariat.org (8.7.5/8.7.3) with ESMTP id IAA00258; Wed, 9 Oct 1996 08:33:19 -0500 Received: from rockvax.rockefeller.edu (rockvax.rockefeller.edu [129.85.1.21]) by wariat.apk.net (8.7.6/8.7.3) with ESMTP id JAA19924; Wed, 9 Oct 1996 09:14:22 -0400 (EDT) Received: from pisa.rockefeller.edu (pisa.rockefeller.edu [129.85.23.103]) by rockvax.rockefeller.edu (8.7.4/8.7.4) with SMTP id JAA01198; Wed, 9 Oct 1996 09:12:54 -0400 (EDT) Received: by pisa.rockefeller.edu (940816.SGI.8.6.9/940406.SGI) id JAA19518; Wed, 9 Oct 1996 09:13:10 -0400 Resent-Date: Wed, 9 Oct 1996 09:13:10 -0400 Date: Wed, 9 Oct 1996 15:11:44 +0200 (MET DST) From: Eugene Leitl X-Sender: ui22204@sun2 To: Wayne Morellini Cc: misc@pisa.rockefeller.edu, " Mr. Dealer" <100576.2741@compuserve.com> Subject: Re:Misc Mailing List is Back In-Reply-To: <199610090235.MAA29146@cq-pan.cqu.EDU.AU> Message-Id: Mime-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Resent-Message-ID: <"SYq6_2.0.vm4.ZJwMo"@pisa> Resent-From: MISC@pisa.rockefeller.edu X-Mailing-List: archive/latest/399 X-Loop: MISC@pisa.rockefeller.edu Precedence: list Resent-Sender: MISC-request@pisa.rockefeller.edu On Wed, 9 Oct 1996, Wayne Morellini wrote: > > [...] > > There are other Forth Processors the SC-32 from silicon composers, the > Harris RTX-200x is still available but only limited versions. The Mup-21 is > a good concept and I can sell you my kit. The others we are still waiting I, too, think MuP21 is good. I still hope to switch to the F21 with minimal conversion effort, should it become avialable in 5-6 months, the end of the time slot alloted to the prototype. Since MuP21 is so very similiar to MuP21, its the logical choice. Particularly, high absolute performance and excellent MIPS/Watt ratio as well as NOP power saving capability are very interesting, since mine is a mobile application demanding sophisticated power management. However (I know I should ask Dr. Ting directly, but he's probably busy and maybe any of you MISCers might already know) - is the MuP21 $350 kit still available? - how many days does one wait for delivery? - is MuP21 available in medium quantities (100-1000 pcs) on short notice? At which prices? - is the MuP21 kit stand-alone? (Meaning, can I just hook up a standard PC keyboard and a (NTSC/PAL) CRT to it and use it for native development platform?) - what does it use for mass storage? Flash memory cards? - can one use the digital I/O ports to do several RS232 by software? - is the only difference between the $100 and the $350 kit is that the latter is assembled? (Meaning, containing the same parts, identical documentation and ROM image?) > for, the Mup-21 execution has been reported to break after something like > 100's of hours, but new packaging that was due soon this time last year and What??? You mean all MuP21 samples one can buy are uncapable of sustained operation??? Can somebody please confirm this observation? > apart from requests nothing else has really been said about it to my > knowledege, this packaging should fix a lot of problems, video resoluation > isn't great 384*2xx. The F-21 and I-21 is supposed to be much better. 384x200 is sufficient for starters. 640x512 would be better, though. > > > >> the page with I21 press release on Jeffs Web site that says it will be > >> available for licencing etc, despite the denial of ITV when I enquired, > > > >I think i21 won't, but F21 will (provided, I'll ever live to see it). > > Like I21 like F-21, but wanted I21 type device. Afair i21 was meant to be proprietary technology, avalable only to iTV. > > > > >> despite Jeff removing the new pages a day or two after I origionally saw > >> them), and THE 32-BIT P32. Announcements of products would be good too. > > > >Seconded fully. > > > >Eugene Leitl > > > > Thanks Eugene. Eugene > Wayne Morellini > waynem1@cq-pan.cqu.edu.au > > -- > > _________________________________________________________________________________ | mailto: ui22204@sunmail.lrz-muenchen.de | transhumanism >H, cryonics, | | mailto: Eugene.Leitl@uni-muenchen.de | nanotechnology, etc. etc. | | mailto: c438@org.chemie.uni-muenchen.de | "deus ex machina, v.0.0.alpha" | | icbmto: N 48 10'07'' E 011 33'53'' | http://www.lrz-muenchen.de/~ui22204 | From MISC-request@pisa.rockefeller.edu Wed Oct 9 15:07:11 1996 Received: from rockvax.rockefeller.edu (rockvax.rockefeller.edu [129.85.1.21]) by eli.wariat.org (8.7.5/8.7.3) with ESMTP id PAA00625; Wed, 9 Oct 1996 15:07:07 -0500 Received: from pisa.rockefeller.edu (pisa.rockefeller.edu [129.85.23.103]) by rockvax.rockefeller.edu (8.7.4/8.7.4) with SMTP id QAA06715; Wed, 9 Oct 1996 16:06:14 -0400 (EDT) Received: by pisa.rockefeller.edu (940816.SGI.8.6.9/940406.SGI) id QAA20531; Wed, 9 Oct 1996 16:06:38 -0400 Resent-Date: Wed, 9 Oct 1996 16:06:38 -0400 Message-ID: <325C05BD.48AB@bbs.wa4yse.ampr.org> Date: Wed, 09 Oct 1996 16:06:21 -0400 From: Andrew Sieber X-Mailer: Mozilla 3.0Gold (Win95; U) MIME-Version: 1.0 To: misc@pisa.rockefeller.edu Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Resent-Message-ID: <"NvURZ2.0.k05.AN0No"@pisa> Resent-From: MISC@pisa.rockefeller.edu Subject: Unidentified subject! X-Mailing-List: archive/latest/400 X-Loop: MISC@pisa.rockefeller.edu Precedence: list Resent-Sender: MISC-request@pisa.rockefeller.edu Eugene Leitl wrote: >- is the MuP21 $350 kit still available? That kit is now $250. >- how many days does one wait for delivery? I mailed my order for the chip and manual on a Tuesday, and they arrived the following Monday. >Particularly, high absolute >performance and excellent MIPS/Watt ratio as well as NOP power saving >capability are very interesting, since mine is a mobile application >demanding sophisticated power management. I'm still not sure I've figured out why NOP gives the ability to save power. It seems to me that all you can do is lower operating voltage to save power. NOPs do nothing to save power, as far as I can see. Does anybody know what an MuP21 does when it executes an invalid opcode? The inversion of odd address and data bits is rather confusing. If I were to add inverters to the odd address pins and two-way inverters to the odd data pins, then would ALL of the inversion mess go away? Would I be able to program it and never have to XOR anything with AAAAA or worry about the inversion stuff at all? If I use the fast I/O space for 15ns sram hookup, and run a program out of it (I know the program would have to be <1k), will the program run faster, since it does not have to access relatively slow dram? If these issues have already been covered in this mailing list and they're stored in the archive, I've had no time lately to read them, so I apologize if these are repeat questions. --Andrew Sieber kd4jtv@bbs.wa4yse.ampr.org From MISC-request@pisa.rockefeller.edu Wed Oct 9 23:12:54 1996 Received: from rockvax.rockefeller.edu (rockvax.rockefeller.edu [129.85.1.21]) by eli.wariat.org (8.7.5/8.7.3) with ESMTP id XAA03352; Wed, 9 Oct 1996 23:12:52 -0500 Received: from pisa.rockefeller.edu (pisa.rockefeller.edu [129.85.23.103]) by rockvax.rockefeller.edu (8.7.4/8.7.4) with SMTP id AAA26169; Thu, 10 Oct 1996 00:10:32 -0400 (EDT) Received: by pisa.rockefeller.edu (940816.SGI.8.6.9/940406.SGI) id AAA21782; Thu, 10 Oct 1996 00:10:59 -0400 Resent-Date: Thu, 10 Oct 1996 00:10:59 -0400 Date: Thu, 10 Oct 1996 06:10:03 +0200 (MET DST) Message-Id: <199610100410.GAA05042@ligeti.inria.fr> From: Christophe Lavarenne To: kd4jtv@bbs.wa4yse.ampr.org CC: misc@pisa.rockefeller.edu In-reply-to: <325C05BD.48AB@bbs.wa4yse.ampr.org> (message from Andrew Sieber on Wed, 09 Oct 1996 16:06:21 -0400) Subject: Re: NOPs, odd bits, timings Resent-Message-ID: <"cvVEc.0.HK5.GT7No"@pisa> Resent-From: MISC@pisa.rockefeller.edu X-Mailing-List: archive/latest/401 X-Loop: MISC@pisa.rockefeller.edu Precedence: list Resent-Sender: MISC-request@pisa.rockefeller.edu > Does anybody know what an MuP21 does when it executes an invalid opcode? Chuck says that the behavior of invalid opcodes is undeterminate. The only way to know, would be to look at the MuP21 chip layout. > NOPs do nothing to save power, as far as I can see. NOPs consume slightly less power than other instructions because the stacks are stable (and the ALU too after the carry chain has settled), so no transistor is switching there, which means with CMOS that only a very small leakage current is consumed. But the instruction decoder, the instruction slot sequencer, the program counter incrementer, the address decoder and memory timing generator are all running and consume power to fetch and execute instructions, even NOPs. A NOP just consumes one instruction slot an cycle with no other side effect. Consuming instruction slots is usefull to reach the next word boundary, which is required for branching instructions, either because branch target adresses are word aligned, or because branch instructions must be in the 1st or 2nd slot not to interfere with the 10 bits target address in the 3rd and 4th slots. Consuming instruction cycles is usefull either to let the carry propagate and settle while the T and S registers are stable, or to tune delays between memory accesses to memory mapped I/Os, or occasionally to let signals settle as for example to correct the A! timing problem of the early MuP21s. > The inversion of odd address and data bits is rather confusing. No more than the conversion between binary/hex/decimal. The confusion maybe comes from the way some cross-compilers are written. Forget bit inversions until you want to transfer your cross-compiled code/data to real memory, and only at that moment invert odd data and address bits. A compiler run by the MuP21 itself does not have to care about bit inversions, exactly as you don't care the voltage encoding of bits on other processors. The only moments when you have to care is when you are accessing external I/O, or when you are looking at the MuP21 pins with a scope. > If I were to add inverters to the odd address pins and two-way inverters > to the odd data pins, then would ALL of the inversion mess go away? Yes, but then the odd pins would be slower, and therefore all the chip would be slower. Why pay continuously at runtime what you can do once at compile time? > If I use the fast I/O space for 15ns sram hookup, and run a program out of it > (I know the program would have to be <1k), will the program run faster, since > it does not have to access relatively slow dram? Instructions and data fetches from fast RAM will be faster, but data fetches from DRAM, slow I/O or byte memory spaces will still have their corresponding timings, because the MuP21's memory timing generator is driven by the address decoder, which also drives the different chip selects. CL From MISC-request@pisa.rockefeller.edu Sun Oct 13 18:21:27 1996 Received: from rockvax.rockefeller.edu (rockvax.rockefeller.edu [129.85.1.21]) by eli.wariat.org (8.7.5/8.7.3) with ESMTP id SAA00232; Sun, 13 Oct 1996 18:21:25 -0500 Received: from pisa.rockefeller.edu (pisa.rockefeller.edu [129.85.23.103]) by rockvax.rockefeller.edu (8.7.4/8.7.4) with SMTP id TAA10294; Sun, 13 Oct 1996 19:20:31 -0400 (EDT) Received: by pisa.rockefeller.edu (940816.SGI.8.6.9/940406.SGI) id TAA05527; Sun, 13 Oct 1996 19:21:06 -0400 Resent-Date: Sun, 13 Oct 1996 19:21:06 -0400 Date: Mon, 14 Oct 1996 09:18:24 +1000 (EST) From: Eddie Matejowsky Subject: f21/itv X-Sender: matejows@pop.qut.edu.au To: MISC@pisa.rockefeller.edu Message-id: <2.2.16.19961014085236.2eaf852e@pop.qut.edu.au> MIME-version: 1.0 X-Mailer: Windows Eudora Pro Version 2.2 (16) Content-type: text/plain; charset="us-ascii" Content-transfer-encoding: 7BIT Resent-Message-ID: <"VNqwb3.0.IM1.VbNOo"@pisa> Resent-From: MISC@pisa.rockefeller.edu X-Mailing-List: archive/latest/423 X-Loop: MISC@pisa.rockefeller.edu Precedence: list Resent-Sender: MISC-request@pisa.rockefeller.edu Dear Jeff, >I am sorry if people are bitter about the slow progress of MISC >chips in the last few years, but we do what we can. I'm not bitter about the slow progress but you just seemed to disappear off the face of the planet for 6 months. A 5 line post to MISC once a month would have given us some idea as to what was happening. >I now think that iTV may develop that "killer app" that is needed >to highlight the MISC technology and get some recognition. It may >in fact give a much needed boost to F21 before things are over. I agree that the f21 should go on the back burner to get iTV chip working ASAP. It's great that CM is getting some real support for a change. Good luck with it all. Eddie, Edward Matejowsky - Queensland University of Technology (Brisbane, Australia) From MISC-request@pisa.rockefeller.edu Mon Oct 14 22:58:27 1996 Received: from rockvax.rockefeller.edu (rockvax.rockefeller.edu [129.85.1.21]) by eli.wariat.org (8.7.5/8.7.3) with ESMTP id WAA09160; Mon, 14 Oct 1996 22:58:25 -0500 Received: from pisa.rockefeller.edu (pisa.rockefeller.edu [129.85.23.103]) by rockvax.rockefeller.edu (8.7.4/8.7.4) with SMTP id XAA21526; Mon, 14 Oct 1996 23:55:11 -0400 (EDT) Received: by pisa.rockefeller.edu (940816.SGI.8.6.9/940406.SGI) id XAA07854; Mon, 14 Oct 1996 23:55:35 -0400 Resent-Date: Mon, 14 Oct 1996 23:55:35 -0400 Date: Mon, 14 Oct 1996 20:54:34 -0700 From: jfox@netcom.com (Jeff Fox) Message-Id: <199610150354.UAA13614@netcom11.netcom.com> To: MISC@pisa.rockefeller.edu Resent-Message-ID: <"n0iLs2.0.cw1.pimOo"@pisa> Resent-From: MISC@pisa.rockefeller.edu Subject: Unidentified subject! X-Mailing-List: archive/latest/424 X-Loop: MISC@pisa.rockefeller.edu Precedence: list Resent-Sender: MISC-request@pisa.rockefeller.edu Dear MISC readers: Please note that Dr. Ting has a new email address. Please make a note for your contacts with Offete Enterprises via email. I will update the information at my web site. Jeff Fox ------------------------- From Dr. C.H. Ting: Dear Forth Engine User: I have a new eMail address here: pting@netcom.com. Please use this address for all our future communication. Thanks, Ting. From MISC-request@pisa.rockefeller.edu Wed Oct 16 13:06:50 1996 Received: from rockvax.rockefeller.edu (rockvax.rockefeller.edu [129.85.1.21]) by eli.wariat.org (8.7.5/8.7.3) with ESMTP id NAA31846; Wed, 16 Oct 1996 13:06:19 -0500 Received: from pisa.rockefeller.edu (pisa.rockefeller.edu [129.85.23.103]) by rockvax.rockefeller.edu (8.7.4/8.7.4) with SMTP id OAA00127; Wed, 16 Oct 1996 14:04:57 -0400 (EDT) Received: by pisa.rockefeller.edu (940816.SGI.8.6.9/940406.SGI) id OAA10458; Wed, 16 Oct 1996 14:03:43 -0400 Resent-Date: Wed, 16 Oct 1996 14:03:43 -0400 Date: Wed, 16 Oct 1996 11:02:41 -0700 From: jfox@netcom.com (Jeff Fox) Message-Id: <199610161802.LAA07020@netcom20.netcom.com> To: MISC@pisa.rockefeller.edu Subject: Logic_design_of_P16 Resent-Message-ID: <"t5DQx1.0.MZ2.zDIPo"@pisa> Resent-From: MISC@pisa.rockefeller.edu X-Mailing-List: archive/latest/425 X-Loop: MISC@pisa.rockefeller.edu Precedence: list Resent-Sender: MISC-request@pisa.rockefeller.edu Dear MISC readers: I wanted to inform people that Dr. Ting has done high level logic simulations of a P32, P16, and P8 that execute the MuP21 instruction set and use different sized internal and external data and address busses. I have not yet figured out exactly what he sent me but it includes an attached (uuencoded) file that uudecodes to (logic 29,051 bytes) I have asked him to send it to me again as this copy didn't decode into ascii on my machine. Jeff Fox From Dr. C. H. Ting: ------------------------------------------------------------------------ To: pting@netcom.com (Peitao Ting), jfox@netcom.com Subject: P16 design Jeff, Just forgot to tell you the progress here. I have P16, P32, and P8 all entered in schematic form and successfully carried them through logic simulation. All of them executes the MuP21 instruction set. P16 has 16-bit data and address buses. P32 has 32-bit data and address buses. P8 has 16-bit internal data and address buses, but only 8-bit external data bus. P16 was also coded in Verilog HDL and simulated successfully. My intention is to move these designs forward through physical simulation and eventually onto silicon, if we can identify applications requiring such processor cores. The text of this paper on the logic design on P16 is attached. I don't know how well it will appear when you read it. You are free to put it on your web site. Let me know if you have any problem. Ting. The following is an attached File item from cc:Mail. It contains information that had to be encoded to ensure successful transmission through various mail systems. To decode the file use the UUDECODE program. --------------------------------- Cut Here --------------------------------- begin 644 Logic Design of P16 text M``46```"``````````````````````````8````#````8@```!@````%```` M>@```0`````(```!>@```!`````)```!B@```"`````"```!J@`````````! M```!J@``;]%,;V=I8R!$97-I9VX@;V8@4#$V('1E>'0!__^``0``P`$``*`! M``"0`0``B/__P(2``&#^@`!@`X``8`.WWV`#@`!@`[O>8`.``&`#O^]@`X`` M8`.][&`#@`!@`[_O\7N`!_,[@`!G,X``SF.``-[#__^]@W__[P,!`]X#`0>< M`P$'.`,!```#`0```P$```,!____`/___P'__X`!___``?__X`'___`!___X M_____/____[_________________________________________________ M____________________________________?____P'___\!____`?___P'_ M__\!____`?___P'___\`____^?=^U/GW?MA+;0P`@````%1%6%1-4U=$```` M````````````````````````````"3$-#0U,;V=I8R!$97-I9VX@;V8@82`Q M-BU":70@36EC"!R M97!L86-E9"!B>2!A9&1E2X@,3`O,3$O.38-#3$N"4EN=')O9'5C=&EO;@T-4#$V(&ES(&$@6]U="!O9B!-=5`R,2!I'1E&5C=71I;VXN("!!;B!E>'1E2!T:&4@4%532"!I M;G-T2!A8V-E7,@:6X@;65M M;W)Y+@T-4"!I2!S879E9"!A M9&1R97-S(&EN(%(@:7,@<&]P<&5D(&)A8VL@:6YT;R!0+B`@5&AE(&5X96-U M=&EO;B!S97%U96YC92!I;G1E2!#04Q,(&-A;B!N;W<@8F4@ M&5C=71E('1H92`[(&-O9&4N("!33$]4,"!C86X@9&\@=7-E9G5L M('=O2`R-2!O9B!T:&4@ M,S(@<&]S2!!8V-E&5R2!A;B!L871C:"!T:&5M(&EN=&\@ M=&AE(%0@2!U;F1E&5C=71I;VXN#0U4:&4@"!A2!.4`T)"4$)"0E!9&1R97-S(')E9VES M=&5R#0D)4@D)"51O<"!O9B!T:&4@'0@8FET M(&EN(%0@2!4(&9O&5R('1O(%0@2`@30T-#3(N,BX)5&AE($1A=&$@#0@ M8FET(&UE;6]R>2!A2!A;F0@82`T+6)I="!C;W5N=&5R($Y0(&%S('1H M92!S=&%C:R!P;VEN=&5R+B`@5&AE(&UE;6]R>2!L;V-A=&EO;B!P;VEN=&5D M('1O(&)Y($Y0(&ES(&1E"X-#2A.;W1E.B`@3U9%4B!C M86YN;W0@8F4@:6UP;&5M96YT960@8F5C875S92!A9G1E2!T:&4@:6YC"X@(%1H92!C;&]C:V5D('!U;'-E(&]N($%,1"!L M871C:&5D('1H92!D871A(&]N('1H92!4+4)U&5C=71I;VX@;V8@=&AE(&UE;6]R>2!I;G-T M2!T:6UE+6]U M="X@($%F=&5R('1H92!M96UO#0@;65M;W)Y(&%R2!S970@9F]R(&%U=&\M:6YC&5C=71I;F<@82!T2!A('-U8G)O=71I;F4@8V%L;"X-#41U2!P M=6QS:6YG(%!#3$LN("!);B!A(&IU;7`O8V%L;"!O<&5R871I;VXL(&YE=R!A M9&1R97-S(&ES(')E860@9G)O;2!T:&4@22!R96=I2!S971T:6YG M('5P('1H92!0($UU>"!A;F0@<'5L2!P M=6QS:6YG($U,1"X@($9R;VT@34$@2!T;R!R96%D(&EN('1H92!N M97AT('=O2!O M<&5R871I;VXN("!)="!I2X@(%1H96X@9&%T82!F M2!C86X@8F4@2X-#51O(&QO860@ M82!M96UO"!S96QE8W0@;&EN92!-4T5,(&UU0T-5&AE(&UA:6X@;65M;W)Y(&ES M('-I;75L871E9"!B>2!A(&UE;6]R>2!B;&]C:R!O9B!S:7AT965N(#$V+6)I M="!34D%-+B`@270@:7,@2X@($$@;65M;W)Y(')E<75E2!P=6QS:6YG($U,1"X@(%1H:7,@<'5L2!W M:6QL(&)E(&EM<&QE;65N=&5D('1O(&%L;&]W(&UE;6]R>2!A8V-E2!F;W(@9&%T82X@($ET('=I;&P@:6YC2!B M>2!P=6QS:6YG('1H92!C;VYT&5R&5R M('-E;&5C=&EO;B!L:6YE(&%N9"!O=&AE&5R('1O(%0@2`@30T)35-%3`D)4V5L96-T(&EN<'5T('1O M('1H92!-02!R96=I&5C=&4@:6YS=')U8W1I;VX@,0T)4TQ/5#()"5!H87-E(#(@;V8@ M=V]R9"!E>&5C=71I;VXL(&5X96-U=&4@:6YS=')U8W1I;VX@,@T)4TQ/5#,) M"5!H87-E(#,@;V8@=V]R9"!E>&5C=71I;VXL(&5X96-U=&4@:6YS=')U8W1I M;VX@,PT)5T-,2S$)"3%S="!P97)I;V0@;V8@<&AA2!I2!A9&1R97-S(')E9VES=&5R($U!#0E- M5T4)"5=R:71E('1O(&UE;6]R>0T)24Q$"0D)3&]A9"!I;G-T'0@=V]R9`T-5&EM:6YG('-I9VYA M;',@5T-,2S$L(%=#3$LR+"!#3$LQ+"!#3$LR(&%N9"!#3$LS(&%R92!!3D0G M960@=&\@=&AE(&EN&5C=71I;VX-#51H92!S97%U96YC:6YG(&QO9VEC(&-O M;G-I2!T M;R!T:&4@'0@=V]R9"!A;F0@;&]A9"!I="!I;G1O($D@2!33$]4,"!A;F0@ M<')O9'5C97,@='=O(&-O;G-E8W5T:79E(&-L;V-K('!U;'-E2!T:6UE2!T:6UE'0@=V]R9"!F2!I;G1O('1H92!)(')E9VES=&5R+B`@4"!R96=I2!A8V-E2!T M:6UE(&$@;65M;W)Y(&%C8V5S2!I2X@($$@'0@=V]R9"!I'0@ M=V]R9"X-#5-,3U0Q+"!33$]4,BP@86YD(%-,3U0S('1R:6=G97(@=&AE:7(@ M&5C=71I;VX@ M;V8@=&AE(&EN&5C=71I;VXN("!4:&ES('-E<75E;F-E(&ES($YE>'17;W)D M+"!A;F0@:70@(&ES('!A8V5D(&)Y(%=#3$LQ(&%N9"!70TQ+,B!G96YE'17;W)D"0D)4V5T=7`)"5=#3$LQ M"5=#3$LR#0T)"0D)35-%3#U0"0E-3$0)24Q$#0D)"0E03$0],0D)"0E00TQ+ M#0U.5T0@:7,@9F5D(&EN=&\@3F5X=%<@=&\@2!D96QA>2!E>'!I'1)('-I9VYA M;',@=VAI8V@@8VQO8VMS('1H92!3;&]T('!I<&4N("!4:')E92!I;G-T&5C=71I;VX@;V8@=&AE(&YE>'0@:6YS=')U8W1I;VXN#0U4;R!D97)I=F5D M('1H92!L;V=I8R!E<75A=&EO;G,@9F]R('1H92!S=&%T:6,@86YD(&1Y;F%M M:6,@8V]N=')O;"!L:6YE2!I2!M86YU86QL>2X@(%1H92!M86EN M(&UE;6]R>2!H87,@,38@;&]C871I;VYS(&%N9"!C86X@:&]L9"!Q=6ET92!E M;&%B;W)A=&4@=&5S="!P2!I;B!0,38@;W!E&%M:6YE9"!T;R!M86ME('-U&5R('-E;&5C=&EN9R!S:6=N86QS(&%N9"!T:&4@'0@,R!W;W)D2`U+"!T:&4@'0@ M;&ET97)A;"!A;F0@861D#0DQ"0D),`D)"0DP"0D)8VAA;F=E(&)E='=E96X@ M,"!A;F0@1D9&1@T),@D)"4I.0R`T"0D),3`P-`D)8V]N9&ET:6]N86P@:G5M M<`T),PD)"4I-4"`S"0D),PD)"6QO;W`@:&5R92!I9B!L:71E2`S#0DQ"0D)2DU0 M(#$)"0DQ"0D)2X-#0U&:6=U Message-ID: <14A91D7FF0@mathsci.msci.memphis.edu> Resent-Message-ID: <"xtkVm3.0.Ld2.DCJPo"@pisa> Resent-From: MISC@pisa.rockefeller.edu X-Mailing-List: archive/latest/426 X-Loop: MISC@pisa.rockefeller.edu Precedence: list Resent-Sender: MISC-request@pisa.rockefeller.edu Jeff Fox said... >I have not yet figured out exactly what he sent me but it includes >an attached (uuencoded) file that uudecodes to (logic 29,051 bytes) >I have asked him to send it to me again as this copy didn't >decode into ascii on my machine. It decodes OK, the problem is it's not plain text. What program did Dr Ting use to write it? It doesn't match any of the ones I tried. On the other hand the text inside is plainly readable if you look at it using something in hex mode. Elko ----------------------------------------------------------------------- Elko Tchernev I want to be a nothing-knower, tchernev@hermes.msci.memphis.edu a little ant on any hill; etchernev@cc.memphis.edu for time is dead, the sun is over tel/fax (901) 678 7304 and there is nothing left to kill. From MISC-request@pisa.rockefeller.edu Wed Oct 16 14:26:20 1996 Received: from rockvax.rockefeller.edu (rockvax.rockefeller.edu [129.85.1.21]) by eli.wariat.org (8.7.5/8.7.3) with ESMTP id OAA32599; Wed, 16 Oct 1996 14:26:16 -0500 Received: from pisa.rockefeller.edu (pisa.rockefeller.edu [129.85.23.103]) by rockvax.rockefeller.edu (8.7.4/8.7.4) with SMTP id PAA06872; Wed, 16 Oct 1996 15:25:02 -0400 (EDT) Received: by pisa.rockefeller.edu (940816.SGI.8.6.9/940406.SGI) id PAA10882; Wed, 16 Oct 1996 15:25:37 -0400 Resent-Date: Wed, 16 Oct 1996 15:25:37 -0400 Date: Wed, 16 Oct 1996 14:23:51 -0500 Message-Id: <199610161923.OAA32563@eli.wariat.org> From: "Robert J. Brown" To: tchernev@hermes.msci.memphis.edu CC: MISC@pisa.rockefeller.edu In-reply-to: <14A91D7FF0@mathsci.msci.memphis.edu> (tchernev@hermes.msci.memphis.edu) Subject: Re: Logic_design_of_P16 Resent-Message-ID: <"Ah9uK1.0.zf2.lQJPo"@pisa> Resent-From: MISC@pisa.rockefeller.edu X-Mailing-List: archive/latest/427 X-Loop: MISC@pisa.rockefeller.edu Precedence: list Resent-Sender: MISC-request@pisa.rockefeller.edu >>>>> "Elko" == Elko Tchernev writes: Elko> Jeff Fox said... >> I have not yet figured out exactly what he sent me but it >> includes an attached (uuencoded) file that uudecodes to (logic >> 29,051 bytes) I have asked him to send it to me again as this >> copy didn't decode into ascii on my machine. Elko> It decodes OK, the problem is it's not plain Elko> text. What program did Dr Ting use to write it? It doesn't Elko> match any of the ones I tried. On the other hand the text Elko> inside is plainly readable if you look at it using something Elko> in hex mode. Elko I uudecoded it into a Unix file and changed all occurances of ^M (the Mac line terminator) to ^J (the Unix line terminator) and then deleted the trash at the top and reformed the paragraphs and it came out fine. -- -------- "And there came a writing to him from Elijah" [2Ch 21:12] -------- Robert Jay Brown III rj@eli.wariat.org http://eli.wariat.org 1 847 705-0424 Elijah Laboratories Inc.; 37 South Greenwood Avenue; Palatine, IL 60067-6328 ----- M o d e l i n g t h e M e t h o d s o f t h e M i n d ------ From MISC-request@pisa.rockefeller.edu Fri Oct 18 22:18:13 1996 Received: from rockvax.rockefeller.edu (rockvax.rockefeller.edu [129.85.1.21]) by eli.wariat.org (8.7.5/8.7.3) with ESMTP id WAA31472; Fri, 18 Oct 1996 22:18:10 -0500 Received: from pisa.rockefeller.edu (pisa.rockefeller.edu [129.85.23.103]) by rockvax.rockefeller.edu (8.7.4/8.7.4) with SMTP id XAA04188; Fri, 18 Oct 1996 23:16:03 -0400 (EDT) Received: by pisa.rockefeller.edu (940816.SGI.8.6.9/940406.SGI) id XAA14416; Fri, 18 Oct 1996 23:16:47 -0400 Resent-Date: Fri, 18 Oct 1996 23:16:47 -0400 Message-ID: <32684804.1090@bbs.wa4yse.ampr.org> Date: Fri, 18 Oct 1996 23:16:20 -0400 From: Andrew Sieber X-Mailer: Mozilla 3.0Gold (Win95; U) MIME-Version: 1.0 To: misc@pisa.rockefeller.edu Subject: speed & schematics Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Resent-Message-ID: <"erb2p2.0.8X3.SW4Qo"@pisa> Resent-From: MISC@pisa.rockefeller.edu X-Mailing-List: archive/latest/428 X-Loop: MISC@pisa.rockefeller.edu Precedence: list Resent-Sender: MISC-request@pisa.rockefeller.edu Christophe Lavarenne wrote: >>the processor must still load operands from memory every fifth cycle, it >>seems to me that even with 15 PICOsecond sram chips the processor would >>still only run at 80 MIPS. >There is no fifth cycle. >The next instruction word is prefetched as soon as possible. I didn't realize the MuP21 had a 20-bit instruction "cache" for the next word that is loaded while the current word is still executing. If it loads while the current word is executing, it'd have to have one, otherwise it'd overwrite the instructions currently being executed. So with sufficiently fast SRAM (like 15ns?), and only ALU and register instructions (other than addition instructions), the MuP21 can in fact be made to run at 100 MIPS? >MIPS has never been a good performance scale to compare processors, and in the >case of miscs it's worse, because the instruction set is so different and >instruction timing depend on voltage and on memory addresses. I realize this; it might take half a dozen MISC instructions to perform the equivalent task of one CISC instruction. As I understand it, the MuP21 can run at 104MHz. I also understand that this clock speed varies slightly based on the supply voltage. What are the minimum and maximum operating frequencies? I just received all the parts I need from Jameco, and I'm going to build a system, sans PCMCIA, using the schematic on page 92 of the Programming Manual, 3rd ed. But it doesn't show how to hook a standard PC keyboard to it. How do I do this? And for my EPROM chip, should I use the SLOW.ROM image file of P21Forth 1.02, or FAST.ROM ? --Andrew From MISC-request@pisa.rockefeller.edu Wed Oct 30 12:19:22 1996 Received: from rockvax.rockefeller.edu (rockvax.rockefeller.edu [129.85.1.21]) by eli.wariat.org (8.7.5/8.7.3) with ESMTP id MAA04064; Wed, 30 Oct 1996 12:19:20 -0600 Received: from pisa.rockefeller.edu (pisa.rockefeller.edu [129.85.23.103]) by rockvax.rockefeller.edu (8.8.2/8.8.2) with SMTP id NAA01299; Wed, 30 Oct 1996 13:12:28 -0500 (EST) Received: by pisa.rockefeller.edu (940816.SGI.8.6.9/940406.SGI) id NAA00497; Wed, 30 Oct 1996 13:12:05 -0500 Resent-Date: Wed, 30 Oct 1996 13:12:05 -0500 Date: Wed, 30 Oct 1996 12:11:18 -0600 Message-Id: <199610301811.MAA03944@eli.wariat.org> From: "Robert J. Brown" To: MISC@pisa.rockefeller.edu CC: rj@eli.wariat.org Subject: Keywords: FORTH MPEG CHICAGO Resent-Message-ID: <"QYWotC.A.sH.yp5dy"@pisa> Resent-From: MISC@pisa.rockefeller.edu X-Mailing-List: archive/latest/429 X-Loop: MISC@pisa.rockefeller.edu Precedence: list Resent-Sender: MISC-request@pisa.rockefeller.edu Looking for experienced Forth programmer with embedded real-time experience to assist in developing firmware for on-chip cpu used as controller for MPEG-2 single chip digital video decoder. Firmware will be responsible for transport stream header processing and general control and sequencing of signal processing hardware on the chip. Experience in developing using Linux as cross-development host. Full-up hardware simulation is in Verilog hosted on Sun/Solaris. Source code control is using RCS/NFS with Gnu emacs as editor. Client is in Northwest suburbs of Chicago. Prefer local talent, but if candidate has reliable internet access for email, NFS, and X11, much work can be done at your site. This is an urgent need! This is to help meet a schedule deadline, so contract duration is thru November, but could extend thru next March. If interested, email either a Postscript or ascii resume, or a URL pointing to an online HTML resume to rj@eli.wariat.org for consideration. -- -------- "And there came a writing to him from Elijah" [2Ch 21:12] -------- Robert Jay Brown III rj@eli.wariat.org http://eli.wariat.org 1 847 705-0424 Elijah Laboratories Inc.; 37 South Greenwood Avenue; Palatine, IL 60067-6328 ----- M o d e l i n g t h e M e t h o d s o f t h e M i n d ------