Subject: Logic_design_of_P16

From: [email-masked] (Jeff Fox)
Date: Wed, 16 Oct 1996 11:02:41 -0700

Dear MISC readers:

I wanted to inform people that Dr. Ting has done high level logic
simulations of a P32, P16, and P8 that execute the MuP21 instruction set
and use different sized internal and external data and address busses.

I have not yet figured out exactly what he sent me but it includes
an attached (uuencoded) file that uudecodes to (logic 29,051 bytes)
I have asked him to send it to me again as this copy didn't
decode into ascii on my machine.

Jeff Fox

From Dr. C. H. Ting:
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To: [email-masked] (Peitao Ting), [email-masked]
Subject: P16 design

Jeff,

Just forgot to tell you the progress here.

I have P16, P32, and P8 all entered in schematic form and successfully carried 
them through logic simulation.  All of them executes the MuP21 instruction set.  
P16 has 16-bit data and address buses.  P32 has 32-bit data and address buses.  
P8 has 16-bit internal data and address buses, but only 8-bit external data bus.

P16 was also coded in Verilog HDL and simulated successfully.  My intention is 
to move these designs forward through physical simulation and eventually onto 
silicon, if we can identify  applications requiring such processor cores.

The text of this paper on the logic design on P16 is attached.  I don't know 
how well it will appear when you read it.  You are free to put it on your web 
site.  Let me know if you have any problem.

Ting.

The following is an attached File item from cc:Mail.  It contains
information that had to be encoded to ensure successful transmission
through various mail systems.  To decode the file use the UUDECODE
program.
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