FISH has a hardware provision for very fast efficient loop constructs.
Because FISH is designed to support digital signal processing (DSP) operations for MPEG-2 audio functions, and such DSP operations are typically performed on vectors of numbers, it is desirable to run the DSP hardware at maximum speed, which is one multiply and accumulate with pre and post barrel shift scaling per machine cycle. To do this requires hardware support for iteration.
The FISH solution to this problem is to have a loop register that inhibits the incrementation of the program counter when the loop register is non-zero. To permit support for looping over subroutine calls rather than restricting its use solely to primative instructions, there is also a where register. The where register must equal the instruction pointer (or program counter), ip, for the loop register to be decremented. This permits hardware loop control to iteratively call the same subroutine, or Forth word.
To permit nested loops to occur, the loop and where registers exist in a stack, called the loop stack, which is controlled by the loop stack pointer, lp. The top loop and where elements of the loop stack are cached in registers.
With this implementation of hardware assisted nested loops, the Forth words i, j, and k may be implemented as follows: i is just the contents of the loop register. j, k, and the rest of the alphabetical loop counters are available by indexing from lp. This requires a hardware adder associated with lp to access the desired loop slot in the loop stack.
To permit interrupts for loop stack overflow and underflow, a width register is provided, analogous to the depth and height registers of the parameter and return stacks.